The present invention relates generally to infrared data communication (IRDC), and more particularly to, a method and apparatus for optimizing a minimum turn around time (MTAT) between the reception and the transmission, as well as between the transmission and the reception, of IRDC data by an infrared device.
Infrared data communication (IRDC) between two infrared (IR) devices is constrained by the half duplex nature of IRDC and certain industry standards, both of which affect the quality and speed of the IRDC. The half duplex nature of IRDC limits the IRDC because only one infrared device can transmit infrared data at a time to the other infrared device, rather than having a simultaneous exchange of such infrared data. Accordingly, speed (throughput) is sacrificed. Moreover, this limitation is further complicated by a Minimum Turn Around Time (MTAT) set forth by industry protocol. Both of these limitations may effect the quality (lost data) or speed (throughput) of the data transmission and their effect must therefore be minimized. Both of these limitations are explained by reference to prior art FIGS. 1, 2, and 3.
FIG. 1 is a prior art block diagram view of an IRDC between two infrared devices. In FIG. 1, a first IR device 5 is in communication with a second IR device 10 using IRDC as the communication means. The first IR device 5 transmits data through frame(s) 15 to the second IR device 10, and in response, the second IR device 10 responds to the first IR device 5 with an acknowledgement frame 20.
The half duplex nature of the IRDC is exemplified in FIG. 2 by an exploded view portion 25 of the first IR device 5 of FIG. 1. In the exploded view portion 25, a first transition (T1) 30 and a second transition (T2) 35 are shown. In T130, the first IR device 5 (FIG. 1) is first receiving 40 (FIG. 2) a frame from the second IR device 10 (FIG. 1) and then transmitting 45 (FIG. 2) an acknowledgement frame to the second IR device 10 (FIG. 1).
Likewise, in T235 (FIG. 2), the first IR device 5 (FIG. 1) is first transmitting 55 (FIG. 2) a frame to the second IR device 10 and then receiving 60 (FIG. 2) an acknowledgement frame. At either transition T1 or T2, the first IR device 5 is able only to perform one transmission with the second IR device 10 at a time (i.e. can only perform at half duplex). Simultaneous transmission by both devices is not possible. Thus, throughput suffers since the IRDC is essentially a timed one-way communication.
This limitation is further complicated by the fact that a MTAT standard must be adhered to during the IRDC between the first 5 and second 10 IR devices (FIG. 1).
MTAT is associated with the minimum time needed between the first reception 40 (FIG. 2) of a frame to the transmission 45 (FIG. 2) of an acknowledgement frame and is depicted by the dashed box 50 for T130 and dashed box 65 for T235 (FIG. 2).
In essence, the first IR device 5 (FIG. 1) must wait the MTAT 50 (FIG. 2) after having received the last byte of a frame from the second IR device 10 (FIG. 1) before the transmission 45 (FIG. 2) of the acknowledgement frame. In the Infrared Data Association publication titled xe2x80x9cSerial Infrared Link Access Protocolxe2x80x9d (IrLAP), version 1.1, dated Jun. 16, 1996 (hereby incorporated by reference), Section 6.6.8 provides the MTAT parameter value to be from 0 to 10 microseconds. This MTAT is generally specified by the receiving device, i.e. the second IR device 10 (FIG. 1).
Thus, the exact time from first reception 40 to first transmission 45 (FIG. 2) which the first IR device 5 (FIG. 1) must implement must be at least that which was specified by the second IR device 10 during the transmission. If this parameter is not followed, and the first IR device 5 does not wait at least the MTAT, there is a risk that the second IR device 10 will not receive the frame 15 properly (e.g. lose data). Furthermore, if the first IR device 5 waits significantly longer than the MTAT 50 (FIG. 2), then throughput can be seriously reduced due to the extra delay time during which no data is being transmitted by either device. There is therefore a need to optimize the actual MTAT to match the standard MTAT prescribed.
A similar problem exists at T235 (FIG. 2). At T2, the first IR device 5 (FIG. 1) first transmits 55 (FIG. 2) the frame to the second IR device 10 (FIG. 1) and then receives 60 (FIG. 2)an acknowledgement frame from the second IR device 10 (FIG. 1). The MTAT associated with this transition is symbolized by box 65 (FIG. 2).
The problems associated with the T2 is that after transmitting 55 the last byte of a frame, the first IR device 5 is allowed a time interval equal to the MTAT to get ready to receive the acknowledgement frame 20 from the second IR device 10. Thus, the second IR device 10 is not allowed to begin its transmission until this MTAT interval has elapsed. Again, the MTAT parameter is set forth in IrLAP with values ranging from 0 to 10 microseconds. The MTAT for T2 must in all cases be no greater than that which was specified by the second IR device 10 during the set up or link between the first IR device 5 and the second IR device 10. Furthermore, minimizing the value of the MTAT 65 is an important design goal because the longer the second IR device 10 is forced to wait before starting its transmission, the more the throughput will be reduced due to the extra delay time during which no data is being transmitted by either device.
Although the key is to optimize the actual MTAT to match the industry parameter, this remains a problem that has not been addressed by conventional IRDC receivers/transmitters and related components. A conventional receiver/transmitter used in IRDC is illustrated in prior art FIG. 3.
FIG. 3 is a block diagram view of a conventional receiver/transmitter of an IR device used in an IRDC. In prior art FIG. 3, the first IR device 5 contains a central processing unit (CPU) 70, conventional components 75 and a receiver/transmitter 80. The CPU 70 is used to control the exchange of data among the components of the first IR device 5. The conventional components 75 are standard control logic and buses used in an IRDC by an IR device, such as those components shown in FIG. 9.0 of the publication (datasheet) xe2x80x9cPC16550D Universal Asynchronous Receiver/Transmitter With FIFOsxe2x80x9d (UART) dated June 1995, hereby incorporated by reference. The UART is manufactured by National Semiconductor Corporation. The receiver/transmitter 80 corresponds to the PC16550D part of the UART and includes the conventional components 85 depicted in FIG. 5.0 of the UART publication. The conventional components 85 thus include the general registers, control logic, latches, buses and buffers as shown in FIG. 5.0 of the UART publication.
Specifically separated from the conventional components 85 in FIG. 3 are the receiver FIFO trigger interrupt 90, receiver FIFO 95 and IDLE interrupt 100, all of which communicate with one another using buses or similar connection lines in the receiver/transmitter 80. The receiver FIFO 95 is used to store the characters from a frame received from another IR device. The receiver FIFO trigger interrupt 90 and the IDLE interrupt 100 are methods used by the UART to inform the CPU 70 that characters from a frame are present in the receiver FIFO 95. In essence, these two methods are used to estimate the proper time to send the characters in the receiver FIFO 95 to acknowledge receipt of the received frame, irrespective of the MTAT. These two methods used by conventional UARTs create serious limitations in optimizing the MTAT of the IRDC.
A first method uses the receiver FIFO trigger interrupt 90 which notifies the CPU 70 when a certain number of characters are present in the receiver FIFO 95. Usually, this number of characters can be specified by the CPU 70 by loading a UART register (not shown) with the particular number of characters.
A second method of informing the CPU 70 that characters are present in the receiver FIFO 95 is by using the IDLE interrupt 100 (also referred to as a FIFO xe2x80x9ctime outxe2x80x9d interrupt) which occurs if at least one character is present in the receiver FIFO 95 and a certain amount of time has elapsed (called the xe2x80x9cIDLE time outxe2x80x9d) during which no character reception has occurred. In some UARTS, the IDLE time out can be specified by the CPU 70 by loading a UART register (not shown).
In general, these two methods inaccurately estimate the appropriate MTAT for transmission of characters received in the receiver FIFO 95 and therefore either send the acknowledgement frame too early (losing data) or too late (losing throughput). Specifically, these two methods affect two broad categories of IRDC, including (1) the MTAT associated with the transition between first receiving a frame to then transmitting an acknowledgement frame (T1 of FIG. 1); and (2) the MTAT associated with the transition between first transmitting a frame to then receiving an acknowledgement frame from another IR device (T2 of FIG. 2).
The problems associated with the MTAT from reception to transmission are mainly due to the manner in which the UART implements the MTAT. Inaccuracies result for three reasons.
First, there is an error due to the UART interrupt latency. That is, when a UART receiver interrupt occurs (either through the receiver FIFO trigger interrupt 90 or the IDLE interrupt 100) there may be some latency before the CPU 70 has a chance to service the interrupt and record the time at which the received characters were read from the receiver FIFO 95. This latency is typically due to other high priority interrupts that may be in the process of being serviced when the UART interrupt occurs. Thus, due to this latency, the actual MTAT from receiving the transmission to transmitting the acknowledgement frame may be greater than what is really necessary because the timer used to time the interval required was started xe2x80x9clate.xe2x80x9d Thus, throughput is sacrificed.
Second, there is an error due to the IDLE time out described above. Recall that the IDLE time out is an amount of time elapsed during which no characters have been received by the receiver FIFO. When the IDLE time out has occurred, the IDLE interrupt informs the CPU 70 that at least one character has been received and that a certain amount of time has elapsed during which no characters have been received. However, the IDLE time out must be accounted for in determining if the prescribed MTAT has elapsed. In the past, the IDLE time out has been subtracted off from the time that the CPU 70 waits after reading the characters out of the receiver FIFO 95 and before starting the transmission of the acknowledgement frame 45 (FIG. 2). The problem with this alternative is that another character might have been received by the UART between the time the IDLE interrupt was triggered and the time the CPU read the characters out of the receiver FIFO 95. Thus, if this alternative is chosen, the MTAT implemented will sometimes be too short by the value of the IDLE time out.
Another alternative is to wait the full MTAT specified by the other IR device after reading the characters out of the receiver FIFO 95 and before starting transmission of the acknowledgement frame 45 (FIG. 2). The problem with this alternative is that the MTAT implemented will in most instances be greater than necessary by the value of the idle time out, and throughput will be sacrificed.
A third error that generally occurs when the UART implements the MTAT from reception to transmission is that errors occur due to the preemption of certain software tasks that implement delays. This error would only be incurred if the CPU 70 has no timer at its disposal which it can program to generate an interrupt at the exact time when the required MTAT has lapsed so that transmission of the acknowledgement frame may be started. If this is the case, then a software routine must implement a hard loop waiting for the MTAT to elapse. However, if that software routine runs from a task which can be preempted by other high priority tasks or interrupts, then that software routine may sometimes be prevented from starting the IRDC at exactly the right time. Thus, the MTAT which is implemented will be greater than necessary.
There further exists certain problems associated with the MTAT between (1) a transmission of a frame to an IR device and (2) the reception from that device of an acknowledgement frame. These problems stem from the fact that the MTAT from transmission to reception cannot be set to a minimum value of zero. The reason for this is that the IR device""s receiver and transmitter are virtually always in close enough proximity to each other such that any data transmitted by the transmitter is automatically received by the receiver. If the UART""s receiver is left enabled while the transmission is in progress, then the data which is transmitted will be xe2x80x9clooped backxe2x80x9d and will appear in the UART""s receiver FIFO 95 (FIG. 3).
Thus, if an IR device employs a standard UART as the receiver/transmitter, the fastest MTAT from transmission to reception that it can possibly implement is accomplished by having the CPU enable the UART""s interrupt when it loads the final data comprised in the transmission frame into a transmission FIFO, and then when the UART interrupt occurs (which indicates that transmission of the last character has now completed) perform the following interrupt service routine which handles the transmit complete condition.
First, if the UART""s receiver was disabled during the transmission (to avoid receiving the loop back data), then re-enable the UART""s receiver. Second, if the UART""s receiver was left enabled during the transmission (and thus the loop back data was received), then flush the UART""s receiver FIFO of the loop back data that is present to avoid misinterpreting the loop back data as data received from the other IR device. When this procedure is performed, it is obvious that the MTAT from transmission to reception cannot be set to zero because the following delay times need to be accounted for. A first delay time must account for the UART interrupt latency since there may be some latency before the CPU 70 has a chance to service the interrupt.
Second, the time to service the interrupt must also be accounted for by the MTAT. These two latency times therefore must be accounted for in the MTAT and the MTAT can therefore not be set to a zero value, in order to be optimized.
A need therefore exists for a method and apparatus that optimizes the MTAT (1) when making the transition from receiving an IRDC frame to transmitting an acknowledgment IRDC frame, and (2) when making the transition from transmitting an IRDC frame to receiving an acknowledgement IRDC frame that overcomes the limitations described above.